Highlights

• A generalized BCH codec capable of correcting up to t errors
• An optimized BCH codec for correcting up to 12 errors
• The maximum codeword length for both codecs is 65535 bits
• For 12 error correction capability, code rates of 0.994 and 0.997,can be can achieved for block lengths of 32768 and 65535, respectively

Target applications

• Error correction for long block lengths when a code rate close to 1 is required
• Ideally suited for concatenated systems with an iterative inner decoder [1,2]:
  • Combining a high rate BCH code with inner Turbo, Turbo product, or Low Density Parity Check (LDPC) code can significantly reduce the error rate flare of the inner code
  • A BCH decoder can correct the low-weight error events that are typical in the flare region of a Turbo or Turbo-like code
  • The BCH code can be tailored to the expected error events at the desired operating point

Benchmarks

Benchmarks were measured for the BCH(16384,16192), BCH(32768,32576) and BCH(65535,65343) on a dual 2.4 GHz Pentium IV computer. The C-code was compiled with the Intel 5.0 compiler, which was set to optimize for Pentium IV. The speed measurements included random error generation, decoding and error checking, so the decoding speeds presented are slightly pessimistic. Decoder speed (i.e., information bit throughput) results are shown in Table 1 for the general decoder, which is flexible in error correction capability and block length. Since the processing varies depending on the number of errors in the codeword, we present the decoding speed that was achieved when the codeword has a specified number of errors.

As speed is sometimes more important than flexibility, we optimized the code to handle the case of BCH(n,n-192) where the maximum block length, n, is 65535. The code can correct up to 12 errors in a codeword. The decoder was benchmarked under the same conditions as the general decoder and the speed results are shown in Table 2.

The decoder speed of the dynamic link library for the decoder suitable for non-Pentium IV and AMD computers may vary from the results presented. This page will be updated when this information is available.

Licensing

Information regarding licensing or a specific codec can be obtained via e-mail (fec-info (at) crc.ca).

References

[1] J. D. Andersen, "Turbo Codes Extended with Outer BCH Code," IEE Electronics Letters, Vol. 3, No. 22, October 1996.

[2] O.Y. Takeshita, O.M. Collins, P.C. Massey and D.J. Costello, "On the Frame-Error Rate of Concatenated Turbo Codes," IEEE Transactions on Communications, Vol. 49, No. 4, pp. 602-608, April 2001.