Various state-of-the-art forward error correction techniques and products have been developed at the Communications Research Centre Canada (CRC) in recent years. These include technologies in the following three categories:
Interleaver Technology
Interleaving is a key component of many digital communication systems involving forward error correction coding. Interleaving the encoded symbols provides a form of time diversity to guard against localized corruption or bursts of errors. In the past the interleaving strategy was usually weakly linked to the selected FEC scheme. Exceptions were concatenated FEC schemes such as concatenated convolutional and Reed-Solomon codes. In this case, the interleaving parameters have been carefully selected to match the error correcting capabilities of the codes involved. Recently, interleavers have become an even more integral part of the code design itself. Such is the case for Turbo and Turbo-like codes. The problem of finding good interleavers for such codes is an on-going area of research.
CRC has developed a number of new interleaver technologies that are useful for both channel interleaving and for designing high-distance Turbo-codes. The various interleaver types are listed below. Golden interleavers and DRP interleavers for Turbo-codes are highlighted further below.
Golden Interleavers
Golden interleavers provide a strategic solution for any error-burst length. With Golden interleavers there is no concept of interleaver depth and no need to design the interleaver for a particular channel type or worst case error-burst length. Three new interleaver designs have been developed based on the golden section. They are called golden relative interleavers, golden interleavers, and dithered golden interleavers. These interleavers have excellent spreading properties and are useful for many applications. The first two interleavers make excellent channel interleavers, while the third has been shown to work well with Turbo-codes.
DRP Interleavers for Turbo-Codes
Dithered Relative Prime (DRP) interleavers are highly structured and ideal for designing low-memory interleaver banks for Turbo-codes. Each interleaver can be stored and implemented (on-the-fly if desired) using only a few parameters. The interleavers are designed to work well with both dual termination and dual tail-biting. The interleaver bank resolution is determined by the dither window size "M". For medium size blocks (i.e. K=256 to 4096) a good M value is 8, so the bank resolution is conveniently in bytes. The structure of DRP interleavers also makes it relatively easy to search the interleaver space for high distance codes.
Interleaver banks are currently available for 4-, 8-, and 16-state codes, with RSC (feedback, feedforward) polynomials of (7,5), (13,15), and (23,35) octal respectively. The block lengths range from 32 to 65536 data bits. The bank resolution depends on the block size, with 8-bit (byte) resolution available for most block lengths of practical interest. Additional interleaver banks will be developed as needed.
Hypercode Technology
HyperCodes (also referred to as enhanced Turbo Product Codes - eTPC) belong to an error-correcting FEC code family that employs iterative decoding.
The basis for HyperCodes is to improve upon the performance of product codes by adding additional coding constraints (often diagonally) to a standard product code. For example, a (17,16)3 product code has dmin = 8; an associated HyperCode of size (17,16)·(17,16)·(18,16) has dmin = 14 - almost doubling the minimum distance of the basic product code, while still maintaining a very regular structure (which is important for high speed hardware implementations).
Although developed by the Communications Research Centre Canada, this technology has been transferred under licence to the private sector. HyperCode hardware encoders/decoders are now available from AHA (www.aha.com) for both ICs and cores.
Ultra-fast Viterbi Codecs for PCs
These are highly efficient implementations of convolutional/Viterbi codecs that run on a Pentium processor under the Windows operating system. Decoding throughput is greater than 6 Mbps with no extra hardware required. A simulation program that uses these codes is also included, allowing performance on an additive white Gaussian noise (AWGN) channel to be measured without any programming whatsoever.
A comprehensive archive of papers on FEC technology is available. These papers are available through the contact persons below or by visiting CRC's FEC Technology website.
CRC's Forward Error Correction Technology is available through licence agreements and cost-recoverable engineering transfer.
Forward Error Correction
Case #10146: High-performance low-complexity error-correcting codes
U.S. Patent #6,145,111
European Common Market Application #98 115 338.0
Canadian Patent Application #2,245,601
Case #10161: Method of enhanced max-log-a posteriori probability processing
U.S. Patent #6,145,114
European Common Market Application #98 115 339.8
Canadian Patent Application #2,245,603
Case #10207: Method and system for high-spread high-distance interleaving for turbo-codes
U.S. Patent #6,728,927
Canadian Patent #2,348,941
Case #10233: High-performance low-memory interleaver banks for turbo-codes
U.S. Patent #6,857,087
Canadian Patent #2,390,096
Case #10291: Code structure, encoder, encoding method, and associated decoder and decoding method and iteratively decodable code structure, encoder, encoding method, and associated iterative decoder and iterative decoding method
U.S. Patent #6,944,803
Canadian Patent Application #2,352,644
Multiuser Detection
Case #10131: Joint detector for multiple coded digital signals
U.S. Patent #6,161,209
Canadian Patent Application #2,201,460
John Lodge
Research Program Manager
Communications Signal Processing
Tel: (613) 998-2284
Fax: (613) 990-6339
E-mail: john.lodge@crc.gc.ca
Jeet Hothi
Director, Technology Transfer Office
Tel: (613) 990-2089
Fax: (613) 990-7671
E-mail: jeet.hothi@crc.gc.ca